• Sashleycat

(Stuff) Thank you for making me laugh. Also a note about memory-write on single CCD AM4 chiplet CPUs


If you came here for the tech bit about memory-write perf, you can skip this and scroll to the bottom.


This really doesn't need any explanation but I'm going to type some stuff because I'm still laughing. I mean, literally, I'm smiling so much it's hilarious. I'm fairly certain it's the same 16-year old that sent a contact form to me when AMD announced B450 wasn't going to support Zen3. Uh, that didn't age well for him. Lol.

As is good form when you catch something like this, you unhook it and throw it back in, so I'll do that now, and then wash my hands because that one was definitely a bottom feeder.

For anyone who's actually interested in the lower memory write performance on single-CCD AM4 Ryzen CPUs (Matisse and Vermeer); it's due to the fact that both the CCD chiplets share the wiring for the memory write back-end. This is to simplify the complexity of traces/circuit on the AM4 package, which was already difficult to re-wire for a chiplet approach. AMD stated that almost all consumer workloads aren't gated by memory-write, (it is more useful to compare copy or read), so the trade-off for the consumer-grade AM4 socket was deemed acceptable.

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