When I was typing my Tech Babble yesterday about Little Navi (Navi 14, RX 5500 XT) I noticed that Nemez has confirmed a 9th Render Backend in the centre of the two groups of 4 RBEs. This would actually mean that Navi 14 has 36 ROPs; not 32 as previously believed.
Now, this doesn't necessarily mean all 36 ROPs are being used concurrently by the GPU, and after talking with Nemez on Twitter; it's likely these are for yield reasons. Essentially, if the chip has a defect in one of the RBE blocks: They can simply re-route the silicon through the 'spare' one. Nemez mentioned that the position of the 9th RBE: in the middle, is so because the distance is about uniform from each of the WGP groups and their Rasterisers: this is the 'spare' block of ROPs
Because AMD typically doesn't disable RBE on their GPUs - even the RX 5600 XT has Navi 10's full compliment of 64 Pixels per clock.
Just an interesting Nugget of information.